Power-on reset circuit for preventing multiple word line selections during power-up of an integrated circuit memory

US5477176A · kind A · utility

Assignee

• Motorola, Inc. · US

Inventors

• Ray L. Chang · Austin, US
• Lawrence F. Childs · Austin, US
• Kenneth W. Jones · Austin, US
• Donovan Raatz · Austin, US
• Stephen T. Flannagan · Austin, US

Key dates

• Filing date: Jun 2, 1994
• Grant date: Dec 19, 1995
• Expiry date: Jun 2, 2014

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03K2017/226
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

A power-on reset circuit (30) for a memory (20) includes a DC model circuit (39), an N.sub.BIAS check circuit (64), and a NAND logic gate (71). A logic low power-on reset signal is provided at power-up of the memory (20) to establish initial conditions in a clock circuit (29) and in row and column predecoders/latches (24, 27). When the power supply voltage, a bandgap reference voltage, and a bias voltage all reach their predetermined voltages, the power-on reset circuit (30) provides a logic high power-on reset signal. In this manner, the power-on reset circuit (30) is assured of providing a logic low power-on reset signal until all of the proper voltage levels are reached. In addition, the power-on reset circuit models a DC circuit equivalent of an address buffer circuit (79) for compensating for process and temperature variations.