Early high level net based analysis of simultaneous switching
US5477460A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 1994 |
| Grant date | Dec 19, 1995 |
| Priority date | — |
| Expiry date | Dec 21, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Switching characteristics of system components are represented and summed so that their effects on the overall system can be observed during the design process. Full simultaneous switching analysis is provided at the earliest levels of design containing minimal level of design data by a method of computing net based simultaneous switching noise levels which supports packages ranging from the smallest chip level to the largest board level. The simultaneous switching activity is computed based on interaction between each driver and each other driver between each component and each other component, with consideration to the spatial inter-relationship net, within a higher level component, to determine each component's drivers effect on itself as well as the coupling effect between drivers on different components. The analysis involves computing simultaneous switching noise by associating a characteristic triangle with each driver application configuration. The characteristic triangle. The height of the triangle, as well as the pitch of the sides of the triangle will be determined by the characteristics of the net. In the early stages of design, a default characteristic triangle is defi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.