Nonvolatile semiconductor memory apparatus
US5477495A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 11, 1994 |
| Grant date | Dec 19, 1995 |
| Priority date | — |
| Expiry date | Apr 11, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile semiconductor memory apparatus of the present invention has a feature that charging of a control gate of a nonselective memory cell is simultaneously executed upon charging of a bit line. That is, in the case of normal reading (random accessing), charging of the control gate of the nonselective memory cell is conducted previously to at least one of source and drain side selective gates. Then, when the threshold value of the memory cell in the case of erasing the cell is judged, in a read mode, charging of the selective gate is started by delaying from the timing of charging the control gate of the nonselective memory cell to negative. That is, the selective gate is closed until the control gate is completely set to a negative testing voltage to prevent the bit line from being discharged. After the control gate is completely set to the negative testing voltage, the selective gate is delayed to be charged so that the selective gate is turned ON.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.