Apparatus and method for optimal error correcting code to parity conversion
US5477551A · kind A · utility
24Cited by
4References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 5, 1994 |
| Grant date | Dec 19, 1995 |
| Priority date | — |
| Expiry date | Jul 5, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This invention relates to the general area of data integrety in digital computers. In particular it relates to digital computer systems having parity checked systems busses and ECC checked memory. This invention increases the performance of such systems by reducing the memory latency incurred in the ECC to parity conversion process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.