Process for fabricating a stashed capacitor in a semiconductor device
US5478769A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 28, 1994 |
| Grant date | Dec 26, 1995 |
| Priority date | — |
| Expiry date | Dec 28, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/714
Abstract
There is a process for fabricating a capacitor of a semiconductor device, distinguished by characteristic steps consisting broadly of laminating an impurity-doped amorphous layer and a pure amorphous layer, alternately and in at least two folds, annealing the multiplicate amorphous layer to polycrystallize it and to diffuse the impurities, utilizing an oxide pattern and a nitride spacer formed at the sidewall of the oxide pattern to form a cylindrical storage electrode consisting of the resulting polysilicon layers, and taking advantage of etch selectivity difference between the doped and undoped polysilicon layers to form grooves in the cylindrical storage electrode. Such storage electrode has a larger surface area than conventional storage electrodes do, in the same space occupied. Therefore, the fabrication process brings about effects that the high integration of semiconductor device can be accomplished and the reliability of device operation can be improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.