Polyimide-insulated cube package of stacked semiconductor device chips
US5478781A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 27, 1994 |
| Grant date | Dec 26, 1995 |
| Priority date | — |
| Expiry date | Oct 27, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/09701
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A cube package of stacked silicon semiconductor chips. To accommodate cube packaging, a metal transfer layer is added over the passivated chip face to bring all of the surface electrical contacts to a common chip edge. The metal transfer layer is insulated from the chip face and from the adjacent chip in the stack by polymer layers having a low dielectric constant, and a thermal expansion coefficient matching that of the stacked chips. An adhesive polymer layer is added to strengthen the bond between the first polymer layers and the adjacent chip in the stack, by deposition of the adhesive layer and partial cure at the wafer level, and then full cure when the chips are stacked together to form the cube.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.