Method and apparatus for attenuating jitter in a digital transmission line
US5479457A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 27, 1993 |
| Grant date | Dec 26, 1995 |
| Priority date | — |
| Expiry date | Aug 27, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0994
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for attenuating jitter in digital signals. A recovered clock is derived from the digital signal and the digital signal is stored in a buffer. The derived clock is input to an input counter which counts a predetermined number of degrees out of phase with an output counter. When the input counter is at a maximum counter value, the output counter value is latched to the address inputs of a ROM look-up table, which outputs a coefficient to a numerically controlled oscillator (NCO). The NCO includes a low frequency portion that adds the coefficient successively to itself and outputs a carry out (CO) signal. A high frequency portion of the NCO receives a high frequency clock and preferably divides down the high frequency clock to a clock frequency which is centered at the desired output frequency. The high frequency portion preferably includes an edge detect circuit that receives the CO signal and adjusts the frequency of the output clock to produce a compensation clock. The compensation clock clocks the output counter which causes a buffer to output a digital signal that is substantially free of jitter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.