Exception handling for prefetched instruction bytes using valid bits to identify instructions that will cause an exception
US5479616A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 3, 1992 |
| Grant date | Dec 26, 1995 |
| Priority date | — |
| Expiry date | Apr 3, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3802
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An exception handling system is used, in an exemplary embodiment, to provide exception handling for prefetched instruction bytes in a pipelined 486-type microprocessor. The microprocessor includes a prefetch unit (22) that controls the loading of a prefetch queue (24), including appending a valid bit to each prefetched instruction byte--this valid bit is conventionally used to notify an instruction decoder (26) that a transferred instruction byte is not valid (such as resulting from a change of flow), causing the decoder to signal a stall condition. According to the exception handling technique of the invention, if the prefetch unit detects that any of a selected number of exception conditions (such as limit violations and page faults) applies to a prefetched instruction byte, it invalidates that instruction byte by clearing the valid bit. When an invalid instruction byte is decoded, the decoder asserts a stall condition that can result from either: (a) the prefetch queue is invalid due to instruction bytes being unavailable or flushing in response to a branch, or (b) an exception condition. An exception processor (30) performs two basic functions: (a) monitoring the prefetch unit,…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.