Mark Bluhm
36Patents
17h-index
17Co-inventors
78Inventor score
Filing activity: Nov 17, 1986 → Oct 31, 2007
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5630149A | Pipelined processor with register renaming hardware to accommodate multiple size registers | Physics | 96 | Expired |
| US5907860A | System and method of retiring store data from a write buffer | Physics | 78 | Expired |
| US5963984A | Address translation unit employing programmable page size | Physics | 68 | Expired |
| US6138230A | Processor with multiple execution pipelines using pipe stage state information to control independent movement of instructions between pipe stages of an execution pipeline | Physics | 65 | Expired |
| US5479616A | Exception handling for prefetched instruction bytes using valid bits to identify instructions that will cause an exception | Physics | 57 | Expired |
| US5630143A | Microprocessor with externally controllable power management | Emerging Cross-Sectional Technologies | 57 | Expired |
| US5632037A | Microprocessor having power management circuitry with coprocessor support | Emerging Cross-Sectional Technologies | 47 | Expired |
| US5584009A | System and method of retiring store data from a write buffer | Physics | 47 | Expired |
| US6205560A | Debug system allowing programmable selection of alternate debug mechanisms such as debug handler, SMI, or JTAG | Physics | 44 | Expired |
| US6073231A | Pipelined processor with microcontrol of register translation hardware | Physics | 41 | Expired |
| US5524234A | Coherency for write-back cache in a system designed for write-through cache including write-back latency control | Physics | 40 | Expired |
| US6088807A | Computer system with low power mode invoked by halt instruction | Emerging Cross-Sectional Technologies | 33 | Expired |
| US5860111A | Coherency for write-back cache in a system designed for write-through cache including export-on-hold | Physics | 28 | Expired |
| US5838897A | Debugging a processor using data output during idle bus cycles | Physics | 27 | Expired |
| US6343363B1 | Method of invoking a low power mode in a computer system using a halt instruction | Emerging Cross-Sectional Technologies | 21 | Expired |
| US4729093A | Microcomputer which prioritizes instruction prefetch requests and data operand requests | Physics | 21 | Expired |
| US5784589A | Distributed free register tracking for register renaming using an availability tracking register associated with each stage of an execution pipeline | Physics | 19 | Expired |
| US5937178A | Register file for registers with multiple addressable sizes using read-modify-write for register file update | Physics | 17 | Expired |
| US5664149A | Coherency for write-back cache in a system designed for write-through cache using an export/invalidate protocol | Physics | 15 | Expired |
| US5596731A | Single clock bus transfers during burst and non-burst cycles | Physics | 14 | Expired |
| US4763253A | Microcomputer with change of flow | Physics | 14 | Expired |
| US5898815A | I/O bus interface recovery counter dependent upon minimum bus clocks to prevent overrun and ratio of execution core clock frequency to system bus clock frequency | Physics | 12 | Expired |
| US5159210A | Line precharging circuits and methods | Electricity | 12 | Expired |
| US5771365A | Condensed microaddress generation in a complex instruction set computer | Physics | 12 | Expired |
| US5375209A | Microprocessor for selectively configuring pinout by activating tri-state device to disable internal clock from external pin | Emerging Cross-Sectional Technologies | 10 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.