Memory access system including a memory controller with memory redrive circuitry
US5479640A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 1993 |
| Grant date | Dec 26, 1995 |
| Priority date | — |
| Expiry date | Jun 30, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/408
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory access system for improving memory access when addressing dynamic random access modules (DRAMs). The memory access system includes a main memory and a memory controller. To improve memory access, both the memory controller and the main memory hardware remember the row address of the last access. Macro operation commands for fetch and store contain the last row address. The main memory hardware redrives that row address to the DRAMs after completion of an access, so that the memory controller need not provide a row address to the memory for each command of a command sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.