Tin-Chee Lo
27Patents
14h-index
40Co-inventors
81Inventor score
Filing activity: Oct 30, 1985 → Aug 4, 2008
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5659551A | Programmable computer system element with built-in self test method and apparatus for repair during power-on | Physics | 87 | Expired |
| US5970052A | Method for dynamic bandwidth testing | Physics | 81 | Expired |
| US5058115A | Fault tolerant computer memory systems and components employing dual level error correction and detection with lock-up feature | Physics | 51 | Expired |
| US5359722A | Method for shortening memory fetch time relative to memory store time and controlling recovery in a DRAM | Physics | 43 | Expired |
| US5661732A | Programmable ABIST microprocessor for testing arrays with two logical views | Physics | 41 | Expired |
| US7058866B2 | Method and system for an on-chip AC self-test controller | Physics | 37 | Expired |
| US5488319A | Latch interface for self-reset logic | Electricity | 36 | Expired |
| US5805789A | Programmable computer system element with built-in self test method and apparatus for repair during power-on | Physics | 32 | Expired |
| US4686392A | Multi-functional differential cascode voltage switch logic | Electricity | 32 | Expired |
| US6839861B2 | Method and system for selecting data sampling phase for self timed interface logic | Electricity | 28 | Expired |
| US5907671A | Fault tolerant system based on voting | Physics | 24 | Expired |
| US6594196B2 | Multi-port memory device and system for addressing the multi-port memory device | Physics | 21 | Expired |
| US5543735A | Method of controlling signal transfer between self-resetting logic circuits | Electricity | 17 | Expired |
| US5138705A | Chip organization for an extendable memory structure providing busless internal page transfers | Physics | 17 | Expired |
| US5479640A | Memory access system including a memory controller with memory redrive circuitry | Physics | 8 | Expired |
| US6910165B2 | Digital random noise generator | Physics | 5 | Expired |
| US5565808A | Latch control circuit | Electricity | 5 | Expired |
| US7587543B2 | Apparatus, method and computer program product for dynamic arbitration control | Physics | 3 | Active |
| US6931492B2 | Method for using a portion of the system cache as a trace array | Physics | 2 | Expired |
| US7739557B2 | Method, system and program product for autonomous error recovery for memory devices | Physics | 1 | Active |
| US5822338A | ECC-compare path of cache directory logic improvements | Physics | 1 | Expired |
| US7275202B2 | Method, system and program product for autonomous error recovery for memory devices | Physics | 1 | Expired |
| US7430698B2 | Method and system for an on-chip AC self-test controller | Physics | 1 | Active |
| US6836840B2 | Slaves with identification and selection stages for group write | Physics | 1 | Expired |
| US7076676B2 | Sequence alignment logic for generating output representing the slowest from group write slaves response inputs | Physics | 1 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.