Three-dimensional multichip package
US5481133A · kind A · utility
443Cited by
4References
13Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 29, 1994 |
| Grant date | Jan 2, 1996 |
| Priority date | — |
| Expiry date | Dec 29, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multichip array package for IC devices with a master semiconductor device supporting and electrically interconnected with a stacked array of subordinate devices. The interconnection structure has a peripheral row of contact pads on the master device. The subordinate devices each have a peripheral row of contact pads that corresponds to the peripheral row on the master device. Openings are provided through the contact pads on the subordinate devices that are in registry. The holes are filled with metal which interconnects the subordinate devices with the master device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.