RISC microprocessor architecture implementing fast trap and exception state
US5481685A · kind A · utility
45Cited by
15References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 21, 1994 |
| Grant date | Jan 2, 1996 |
| Priority date | — |
| Expiry date | Nov 21, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7842
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Fast trap mechanism for a microprocessor, wherein a vector trap table is maintained which contains space for a plurality of instructions in each table entry. When a fast trap occurs, control is transferred directly into the table entry corresponding to the trap number. The trap handler can be located completely inside the table entry, or it can transfer control to additional handler code.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.