Inversion implant isolation process
US5482874A · kind A · utility
1Cited by
20References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 19, 1993 |
| Grant date | Jan 9, 1996 |
| Priority date | — |
| Expiry date | Nov 19, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/177
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for improving the performance of a walled emitter bipolar-junction transistor and the improved walled emitter bipolar junction transistor resulting therefrom are disclosed. The method involves the incorporation of a p-type dopant, preferably boron, at the intersection of the isolation oxide and the emitter-base region. The selective implantation does not affect the transistor's function in any significant way, does not complicate the fabrication process to any significant degree and eliminates known problems of intrinsic base boron segregation and oxide charges in known walled emitter bipolar junction transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.