Method for fabricating insulated gate field effect transistor having subthreshold swing

US5482878A · kind A · utility

Assignee

• Motorola, Inc. · US

Inventors

• Vida Ilderem Burger · Phoenix, US
• Michael H. Kaneshiro · Chandler, US
• Diann Dow · Chandler, US
• Kevin M. Klein · Tempe, US
• Michael Masquelier · Phoenix, US
• E. James Prendergast · Phoenix, US

Key dates

• Filing date: Apr 4, 1994
• Grant date: Jan 9, 1996
• Expiry date: Apr 4, 2014

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

Insulated gate field effect transistors (10, 70) having process steps for setting the V.sub.T and a device leakage current which are decoupled from the process steps for providing punchthrough protection, thereby lowering a subthreshold swing. In a unilateral transistor (10), a portion (37, 45) of a dopant layer (25, 30) between a source region (48, 51) and a drain region (49, 52) serves as a channel region and sets the V.sub.T and the device leakage current. A halo region (34, 39) contains the source region (48, 51) and sets the punchthrough voltage. In a bilateral transistor (70), both a source region (83, 86) and a drain region (84, 87) are contained within halo regions (75, 74, 79, 81). A portion (76, 82) of a dopant layer (25, 30) sets the V.sub.T and a leakage current, whereas the halo region (75, 79) sets the punchthrough voltage.