Programmable logic device with logic block outputs coupled to adjacent logic block output multiplexers
US5483178A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 4, 1994 |
| Grant date | Jan 9, 1996 |
| Priority date | — |
| Expiry date | Mar 4, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1737
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable logic device is provided that contains a plurality of logic array blocks arranged in rows and columns. The logic array blocks are interconnected with horizontal conductors in each row and vertical conductors in each column. The logic array blocks and the interconnections between conductors are configured using programmable logic. Some of the programmable logic is used to selectively connect logic array block input terminals to the horizontal conductors. Additional logic in each column is used to selectively connect the horizontal conductors to either logic array block output terminals from the same column or logic array block output terminals from an adjacent column. The additional logic prevents certain interconnection pathways from being blocked and increases the overall flexibility of the interconnection scheme of the programmable logic device, thereby improving device performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.