Rakesh Patel
152Patents
29h-index
61Co-inventors
93Inventor score
Filing activity: Feb 23, 1993 → Nov 8, 2013
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5371422A | Programmable logic device having multiplexers and demultiplexers randomly connected to global conductors for interconnections between logic elements | Electricity | 269 | Expired |
| US5350954A | Macrocell with flexible product term allocation | Electricity | 213 | Expired |
| US5483178A | Programmable logic device with logic block outputs coupled to adjacent logic block output multiplexers | Electricity | 197 | Expired |
| US6184707A | Look-up table based logic element with complete permutability of the inputs to the secondary signals | Physics | 176 | Expired |
| US6407576B1 | Interconnection and input/output resources for programmable logic integrated circuit devices | Electricity | 147 | Expired |
| US5949710A | Programmable interconnect junction | Electricity | 142 | Expired |
| US6020758A | Partially reconfigurable programmable logic device | Electricity | 130 | Expired |
| US6020760A | I/O buffer circuit with pin multiplexing | Electricity | 117 | Expired |
| US7701252B1 | Stacked die network-on-chip for FPGA | Electricity | 101 | Active |
| US6285211A | I/O buffer circuit with pin multiplexing | Electricity | 97 | Expired |
| US5369314A | Programmable logic device with redundant circuitry | Electricity | 88 | Expired |
| US6467017B1 | Programmable logic device having embedded dual-port random access memory configurable as single-port memory | Physics | 87 | Expired |
| US5650734A | Programming programmable transistor devices using state machines | Physics | 84 | Expired |
| US6750675B2 | Programmable logic devices with multi-standard byte synchronization and channel alignment for communication | Electricity | 74 | Expired |
| US6025737A | Circuitry for a low internal voltage integrated circuit | Electricity | 71 | Expired |
| US6604228B1 | Technique of fabricating integrated circuits having interfaces compatible with different operating voltage conditions | Electricity | 63 | Expired |
| US6724328B1 | Byte alignment for serial data receiver | Electricity | 63 | Expired |
| US5870410A | Diagnostic interface system for programmable logic system development | Physics | 56 | Expired |
| US6011744A | Programmable logic device with multi-port memory | Electricity | 55 | Expired |
| US5821773A | Look-up table based logic element with complete permutability of the inputs to the secondary signals | Electricity | 50 | Expired |
| US6281704A | High-performance interconnect | Electricity | 48 | Expired |
| US6147511A | Overvoltage-tolerant interface for integrated circuits | Electricity | 40 | Expired |
| US6175952A | Technique of fabricating integrated circuits having interfaces compatible with different operating voltage conditions | Electricity | 38 | Expired |
| US7227918B2 | Clock data recovery circuitry associated with programmable logic device circuitry | Electricity | 38 | Expired |
| US6353552B2 | PLD with on-chip memory having a shadow register | Electricity | 35 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.