Semiconductor integrated device and wiring correction arrangement therefor
US5483490A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 1993 |
| Grant date | Jan 9, 1996 |
| Priority date | — |
| Expiry date | Dec 1, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An arrangement is provided for preventing DC defects in a memory or logic device after switching to a redundant circuit, improving the product yield of the device by cutting a leakage current path through a defective element or circuit. The cutting points formed by the predetermined wirings as a whole or a part thereof are provided to the device. A probe test of the formed chip is executed under the wafer condition by predetermined test equipment, and wiring correction data regarding the cutting of the cutting points is generated based on the result of test. Moreover, this wiring correction data is transmitted in an on-line fashion to the wiring correction equipment so that the corresponding cutting points can be cut. The wiring correction equipment can be formed by an EB direct writing apparatus, an FIB apparatus or a laser repair apparatus. With this arrangement, the leakage current path formed by a defective element or circuit left unused in conventional circuits is cut, and the product yield of the device is raised significantly. This arrangement can be used for a variety of memory or logic devices, including DRAMs, SRAMs, multiport memories and gate arrays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.