Element joining pad for semiconductor device mounting board
US5485352A · kind A · utility
4Cited by
5References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 16, 1994 |
| Grant date | Jan 16, 1996 |
| Priority date | — |
| Expiry date | Dec 16, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K1/092
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An element joining pad for a semiconductor device mounting board includes a thick-film metalized layer, a barrier layer, and a Ni plating layer. The thick-film metalized layer is selectively formed on a low-temperature sintered board and consists of one of a metal and an alloy which can be sintered at 500.degree. C. or more and 1,200.degree. C. or less. The barrier layer is formed on the thick-film metalized layer and constituted by one of a Rh plating layer and a Ru plating layer. The Ni plating layer is formed on the barrier layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.