Bus interconnect circuit including port control logic for a multiple node communication network
US5485458A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 5, 1993 |
| Grant date | Jan 16, 1996 |
| Priority date | — |
| Expiry date | Mar 5, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4226
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bus interconnect device including port control logic for a communication network having a plurality of multi-port nodes that are connected with point-to-point links. Each node includes a transceiver, turn around logic that controls the transceiver, and a dominant logic physical bus that is coupled to all ports in a node. A bus interconnect device includes a first port, a second port, and a point-to-point link between the first and second ports. During arbitration, from the viewpoint of each node, the bus interconnect devices cause the plurality of physical buses to appear to be a single logical bus having a dominant logic. During data transfer following arbitration, the bus interconnect devices are configured to transmit data from the winning node to all other nodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.