Method of fabrication of protected programmable transistor with reduced parasitic capacitances

US5486480A · kind A · utility

Assignee

• North American Philips Corporation · US

Inventor

• Teh-Yi J. Chen · Cupertino, US

Key dates

• Filing date: Oct 28, 1994
• Grant date: Jan 23, 1996
• Expiry date: Oct 28, 2014

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/307

Abstract

A programmable transistor includes impurity regions to reduce punch-through and soft-write phenomena. In order to provide a fast operation, the impurity regions are arranged with regard to one another so that parasitic capacitances at junctions of impurity regions of mutually opposite conductivity type are minimized. For these purposes, the transistor comprises a charge storage region over a channel region in a main semiconductor zone of a first conductivity type located between a source and a drain of a second conductivity type opposite to the first. A first impurity zone of the first conductivity type, substantially laterally contiguous with the drain, extends into the channel region and is more heavily doped than the main zone. The drain includes a heavily doped third impurity region and a lightly doped second impurity region that lies at least mainly between the third region and the zones.