Method of forming multilayered wiring structure in semiconductor device
US5486492A · kind A · utility
81Cited by
9References
40Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 29, 1993 |
| Grant date | Jan 23, 1996 |
| Priority date | — |
| Expiry date | Oct 29, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76879
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a via structure having good characteristics in a semiconductor device having a multilayered wiring structure includes forming a thin film including a high melting point metal or a high melting point metal compound on at least the side wall of a via hole before a via plug including Al or an Al alloy is formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.