Adder-based base cell for field programmable gate arrays
US5488315A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 5, 1995 |
| Grant date | Jan 30, 1996 |
| Priority date | — |
| Expiry date | Jan 5, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/4812
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An adder-based base cell (10) is provided for field programmable gate arrays. The base cell (10) includes a first inverter (13) operable to receive a first input signal (A). A first NAND gate (12) is coupled to the first inverter (13) and is operable to receive a second input signal (B). A first 2:1 multiplexer (14) is coupled to the first NAND gate (12) and is operable to receive a third input signal (C). The output of the first 2:1 multiplexer (14) represents a first function (F1). A second inverter (17) is operable to receive a fourth input signal (D). A second NAND gate (16) is coupled to the second inverter (17) and is operable to receive a fifth input signal (E). An XOR gate (18) is coupled to the second NAND gate (16), is operable to receive a sixth input signal (F), and is coupled to the first 2:1 multiplexer (14). The output of the XOR gate represents a partial sum function (PS.sub.-- 1). A second 2:1 multiplexer (19) is operable to receive a seventh input signal (G), is operable to receive an eighth input signal (H) and is coupled to the XOR gate (18). The output of the second 2:1 multiplexer (19) represents a second function (F2).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.