High performance extended data out
US5490114A · kind A · utility
37Cited by
15References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 22, 1994 |
| Grant date | Feb 6, 1996 |
| Priority date | — |
| Expiry date | Dec 22, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high performance latch for read and write operations in RAM having a Complimentary Interlock circuit that eliminates the need for external timing to the RAM which might limit its high performance operation. For both read and write operations, the complementary interlock circuit extends a latching signal until valid data appears on the read or write data lines, thus preventing a valid data miss.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.