Reduced stress terminal pattern for integrated circuit devices and packages
US5491364A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 1994 |
| Grant date | Feb 13, 1996 |
| Priority date | — |
| Expiry date | Aug 31, 2014 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A terminal pattern is provided for an integrated circuit device, such as a ball grid array package or an integrated circuit flip chip. The terminal pattern is composed of a number of terminals arranged in concentric arrays, each array having a substantially circular shape and being composed of a number of terminals. The terminal pattern is composed of at least two arrays, and more typically three or more arrays. When the integrated circuit device is mounted to its intended substrate, the individual terminals of the terminal pattern each register with and are soldered to a corresponding conductor of a conductor pattern formed on the substrate. A significant advantage is that, due to the terminals of the terminal pattern being arranged in concentric arrays, a smaller maximum width for the terminal pattern is achieved than possible with a conventional rectangular terminal pattern having the same number of terminals. As such, the terminal pattern and the resulting solder joints between the terminal pattern and its corresponding conductor pattern exhibit improved fatigue life as compared to the conventional rectangular terminal pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.