I.sub.DDQ -testable RAM
US5491665A · kind A · utility
20Cited by
2References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 31, 1994 |
| Grant date | Feb 13, 1996 |
| Priority date | — |
| Expiry date | Aug 31, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic circuit includes an array of a number of memory cells that are functionally organized in rows and columns. The circuit includes test circuitry that is selectively operative to access all cells of the array in parallel. An I.sub.DDQ -test then discovers whether or not there is a defect in any of the cells. This results in a test circuit which is faster, more efficient and more economical than previously-available circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.