Inventor · Waterloo, ON, CA

Manoj Sachdev

36Patents
9h-index
28Co-inventors
75Inventor score

Filing activity: Aug 31, 1994 → Oct 31, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US8363455B2 Eight transistor soft error robust storage cell Electricity 31 Active
US7583555B2 Robust and Efficient dynamic voltage scaling for portable devices Emerging Cross-Sectional Technologies 24 Expired
US8536898B2 SRAM sense amplifier Physics 23 Active
US5491665A I.sub.DDQ -testable RAM Physics 20 Expired
US5625300A Separate I.sub.DDQ -testing of signal path and bias path in an IC Physics 14 Expired
US5495448A Memory testing through cumulative word line activation Physics 14 Expired
US8072797B2 SRAM cell without dedicated access transistors Physics 11 Active
US5831463A MOS master-slave flip-flop with reduced number of pass gates Electricity 11 Expired
US7372721B2 Segmented column virtual ground scheme in a static random access memory (SRAM) circuit Physics 9 Active
US6134688A Electronic device selectably operable as a sequential logic circuit or a combinatorial logic circuit and circuit testing method Physics 8 Expired
US6445235B1 Iddq-testable uni-directional master-slave Physics 8 Expired
US6765414B2 Low frequency testing, leakage control, and burn-in control for high-performance digital circuits Physics 8 Expired
US7200057B2 Test for weak SRAM cells Physics 8 Expired
US7643329B2 Asymmetric four-transistor SRAM cell Physics 6 Active
US5969653A Testing control signals in A/D converters Electricity 5 Expired
US7613067B2 Soft error robust static random access memory cells Physics 5 Active
US6127838A IDDQ testable programmable logic arrays Physics 5 Expired
US5831986A Fault-tolerant memory address decoder Physics 4 Expired
US6429711B1 Stack-based impulse flip-flop with stack node pre-charge and stack node pre-discharge Electricity 4 Expired
US5751141A I.sub.DDQ -testing of bias generator circuit Electricity 3 Expired
US6369631B1 High performance impulse flip-flops Electricity 3 Expired
US5781025A Method for testing an electronic circuit by logically combining clock signals, and an electronic circuit provided with facilities for such testing Physics 3 Expired
US11082241B2 Physically unclonable function with feed-forward addressing and variable latency output Electricity 2 Active
US8488403B2 Sense-amplification with offset cancellation for static random access memories Physics 2 Active
US6366147B2 High performance impulse flip-flops Electricity 2 Expired

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.