PNP punchthrough-assisted protection device for special applications in CMOS technologies
US5493133A · kind A · utility
21Cited by
3References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 17, 1995 |
| Grant date | Feb 20, 1996 |
| Priority date | — |
| Expiry date | May 17, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/711
Abstract
A protection circuit (40) providing positive and negative stress protection. A lateral PIN (58) assists in the triggering of a silicon-controlled rectifier (60) for positive stress protection. A vertical PNP (62) provides negative stress protection. A Schottky diode 64 may be used for biasing a n-well (44) to prevent latchup.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.