Transistor device with increased breakdown voltage
US5493149A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 23, 1994 |
| Grant date | Feb 20, 1996 |
| Priority date | — |
| Expiry date | Feb 23, 2014 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/096
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A bipolar lateral device is disclosed having a high BV.sub.ceo. The device is formed according to a single polysilicon process. In one embodiment silicide is excluded from the surface of the N+ doped polysilicon protecting the N- base width region of the device and the resulting device has a BV.sub.ceo of 8 to 10 V. In another embodiment, the silicide is excluded from the surface of the polysilicon protecting the n-base width region and the polysilicon is maintained as intrinsic polysilicon. The resulting device has a BV.sub.ceo of about 20 V. The devices are useful as voltage clamping devices in programmable logic circuits which must withstand a collector to emitter reverse bias voltage that is sufficient to program either vertical fuse or lateral fuse devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.