Software assisted hardware TLB miss handler
US5493660A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 6, 1992 |
| Grant date | Feb 20, 1996 |
| Priority date | — |
| Expiry date | Oct 6, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a software-assisted hardware TLB miss-handler which is designed to reduce the TLB miss penalty while being low cost to implement and requiring little chip area or complexity. When a TLB miss occurs, the HW TLB miss handler of the present invention computes a physical address of a page table entry located in a special hardware-visible table based on a missing virtual address. It accesses the page table entry and checks for a correct translation and status information. If correct, a physical page address and protection information of the page table entry are inserted into the TLB. The original virtual address is re-translated and normal program execution continues. If the correct translation and status are not found, the HW TLB miss-handler will not insert the entry and will trap to a more sophisticated SW TLB miss handler. A pointer to the page table entry is passed to the SW TLB miss handler so that the page table address need not be recomputed. Thus, the HW TLB miss-handler of the present invention services the simplest and most common TLB misses very quickly, reducing the overall TLB miss penalty. The slower SW TLB miss handler services the more com…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.