Stacked ferroelectric memory cell
US5495117A · kind A · utility
45Cited by
9References
34Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 10, 1994 |
| Grant date | Feb 27, 1996 |
| Priority date | — |
| Expiry date | Jun 10, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/68
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A ferroelectric memory cell has an FET covered by an insulation layer and a ferroelectric capacitor located thereover. An interconnect couples an upper plate of the ferroelectric capacitor to a source/drain of the transistor. In a method of forming the cells, after the transistor is fabricated, the bottom electrode and ferroelectric dielectric are established, but the top capacitor electrode is not added until a further layer of insulation is added over the ferroelectric and windows are opened in it. One window is for the top electrode and another window is to one source/drain region of the FET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.