Memory testing through cumulative word line activation
US5495448A · kind A · utility
14Cited by
4References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 6, 1995 |
| Grant date | Feb 27, 1996 |
| Priority date | — |
| Expiry date | Mar 6, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An SRAM has a plurality of respective memory cells coupled to a respective one of a plurality of word lines and to a pair of bit lines. The SRAM comprises I.sub.DDQ test means to render the word lines active in parallel by cumulatively increasing a number of active ones among the word lines. This permits the writing of a specific logic state in all cells of a column through the tiny bit line drivers that are progressively assisted by the cells already written, thus avoiding the use of additional heavy write circuitry for I.sub.DDQ test purposes only.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.