Method and apparatus for testing integrated circuits
US5495486A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 11, 1992 |
| Grant date | Feb 27, 1996 |
| Priority date | — |
| Expiry date | Aug 11, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3185
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Individual elements of an integrated circuit such as storage elements, (for example, latch elements), can be selectively coupled to select lines and probe lines. During normal operation the latches are not connected to the select lines and behave as a normal latch. During a write/control test operation, the latch is connected to a select line and data placed on the select line is provided to an input of latch. Thereafter, the latch is placed into a latching state in response to the probe line and the clock signal, latching the data provided from the select line into latch. In order to read/observe data, the clock line and probe line are controlled to route data onto the associated select line. In one embodiment the probe line controls a transistor switch that connects the select line to the input of the latch. The probe line also controls a transmission gate which is placed in the latch to toggle the latch between a latching condition and a non-latching condition, in response to signals on the probe line. Preferably each select line and probe line are attached to a plurality of elements and each element is connected to one select line and one probe line. Thus, by placing signals on…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.