Checkpoint synchronization with instruction overlap enabled
US5495590A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 1995 |
| Grant date | Feb 27, 1996 |
| Priority date | — |
| Expiry date | Jun 7, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1407
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An instruction processing system and method which utilizes instruction completion to isolate errors, including those in the post-completion processing of operand stores, to an interval between checkpoints, while allowing the processing of checkpointing instructions to be overlapped with that of other instructions. Checkpoints are established before and after such instructions, and all processing (including that of operand stores) from before a checkpoint must be done prior to allowing instruction completion to move beyond the checkpoint. Nevertheless, instructions from beyond a checkpoint are allowed to be processed up to the point of completion while waiting for the checkpoint to be cleared. The point at which instructions must wait on a prior checkpoint is thus moved to the final phase of instruction processing (instruction completion), at significant performance advantage over a conventional implementation in which this waiting is done at instruction fetch, decode, or execution time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.