Method for fabricating a self-aligned T-gate metal semiconductor field effect transistor
US5496779A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 1994 |
| Grant date | Mar 5, 1996 |
| Priority date | — |
| Expiry date | Dec 19, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28587
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method of fabricating a metal semiconductor field effect transistor, comprising the steps for, forming the channel using an ion-implantation, sequentially forming a first insulator layer at a first predetermined temperature and a second insulation layer at second predetermined temperature over the surface of the substrate, etching the first and second insulation layers using a gate pattern of a photo-resist pattern to expose the channel region as a mask, forming a refractory metal over the surface of the first and second insulation layer add the exposed channel region, etching the refractory metal, thereby dividing it into two parts of which one is formed on the channel region and the other is formed on the second insulation layer, selectively etching the first and second insulation layers to lift-off the refractory metal over the first and second insulation layers, thereby forming a gate of a T-shape on the channel region, ion implanting Si into a substrate using the gate and a channel pattern of a photo-resist film to form a self-aligned high concentration ion implantation region, forming a third insulation layer for preventing As of evaporation, carrying out a rap…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.