Silicon-on-insulator gate-all-around MOSFET devices and fabrication methods
US5497019A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 22, 1994 |
| Grant date | Mar 5, 1996 |
| Priority date | — |
| Expiry date | Sep 22, 2014 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/135
Abstract
A gate-all-around (GAA) metal-oxide-semiconductor field-effect transistor (MOSFET) includes a source, channel and drain surrounded by a top gate and a buried bottom gate, the latter of which also has application for other buried structures and is formed on a bottom gate dielectric which was formed on source, channel and drain semiconductor layer. After forming a planar bottom insulator layer on the bottom gate and bottom gate dielectric, the device is flip-bonded to an oxide layer of a bulk silicon wafer, thereby encapsulating the buried bottom gate electrode in insulating oxide. The semiconductor layer forms the source, drain and channel in a mesa structure on which is deposed a top gate dielectric, a top gate, and top gate insulator as well as four conductors for connecting to the source, drain, top gate and bottom gate. The latter two electrodes can be independently controlled or commonly controlled for enhanced operation of GAA MOSFET having improved isolation and reduced parasitic capacitance due to the use of encapsulating insulation layers of the merged wafer consisting of two bonded wafers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.