Flip-flop circuit having low standby power for driving synchronous dynamic random access memory
US5497115A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 1994 |
| Grant date | Mar 5, 1996 |
| Priority date | — |
| Expiry date | Apr 29, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4096
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flip-flop circuit for driving an input circuit of a synchronous dynamic random access memory (SDRAM) including a complementary pair of data inputs for receiving data pulses, a clock input for receiving clock pulses, a capture latch circuit for capturing a bit, having a pair of complementary inputs and a pair of complementary outputs, apparatus for applying data pulses from the complementary data inputs to the inputs of the capture latch, apparatus for triggering the capture latch from the clock pulses, and apparatus for connecting the complementary outputs to each other through a bidirectional holding latch, whereby during coincidence of a rising edge of a clock pulse and the presence of a data pulse of one polarity, the capture latch is enabled to store a bit corresponding to the data pulse, and to drive the pair of complementary outputs, and following the leading edge of a clock pulse and the one polarity of the data pulse the complementary outputs remain driven by the holding latch. The invention utilizes lower standby power in comparison to prior art flip-flop circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.