Superscalar risc instruction scheduling
US5497499A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 1994 |
| Grant date | Mar 5, 1996 |
| Priority date | — |
| Expiry date | Mar 29, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3856
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a computer having an instruction execution unit with a register file accessed by read address ports and for storing instruction operands. A data dependance check circuit is included for determining data dependencies between the instructions. A tag assignment circuit generates one of more tags to specify the location of operands, based on the data dependencies determined by the data dependance check circuit. A set of register file port multiplexers select the tags generated by the tag assignment circuit and pass the tags onto the read address ports of the register file for storing execution results.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.