Method of producing semiconductor device layer layout
US5498579A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 1994 |
| Grant date | Mar 12, 1996 |
| Priority date | — |
| Expiry date | Jun 8, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/70283
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method of enhancing the lithographic resolution of randomly laid out isolated structures is disclosed. A first mask comprises an active layer with isolated features such as gates. Portions of the active layer have a reduced dimension typical of periodic structures. The first mask additionally has complementary features provided along side the reduced active features to provide periodicity. In this way, the resolution of the lithographic process is enhanced, and other enhanced resolution technologies additionally can be used to best advantage to form a patterned photosensitive layer having isolated features of reduced width. The photosensitive layer is then exposed to a second mask which exposes the complementary features so that they are removed from the latent image in the photosensitive layer. This second exposure also further improves resolution by enhancing the contrast between exposed and unexposed regions. A method is disclosed for automatically providing random logic device layouts having the complementary features, as well as for providing a layout for the second mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.