Transistor layout for semiconductor integrated circuit
US5498897A · kind A · utility
4Cited by
2References
8Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Jul 1, 1994 |
| Grant date | Mar 12, 1996 |
| Priority date | — |
| Expiry date | Jul 1, 2014 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/927
Abstract
A semiconductor integrated circuit comprising a MOSFET having a metal wiring layer formed via an insulating film above and along the gate electrode of the MOSFET. The MOSFET is structured such that its channel length is small or channel width is large, and an input signal is applied from at least both end sides of the gate electrode thereof. Since the metal wiring layer for the input signal is formed on the gate electrode of the MOSFET, high-speed operation is possible without increasing the layout area. FIG. 1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.