Implementation of redundancy on a programmable logic device
US5498975A · kind A · utility
95Cited by
11References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 4, 1993 |
| Grant date | Mar 12, 1996 |
| Priority date | — |
| Expiry date | Nov 4, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00392
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An improved architecture and method of operation for providing redundancy in programmable logic devices. Spare columns or rows of logic blocks 115 and switch boxes 140 are employed to replace columns or rows of logic blocks containing one or more defective logic blocks. Associated logic enable the device to bypass a column or row of logic blocks 115 containing one or more defective logic blocks 115 and to switch in a spare column or row of defect-free logic blocks 115 as replacement.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.