Srinivas T. Reddy
102Patents
34h-index
54Co-inventors
93Inventor score
Filing activity: Apr 14, 1992 → Sep 26, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5689195A | Programmable logic array integrated circuit devices | Electricity | 391 | Expired |
| US6215326A | Programmable logic device architecture with super-regions having logic regions and a memory region | Electricity | 263 | Expired |
| US5744991A | System for distributing clocks using a delay lock loop in a programmable logic circuit | Electricity | 180 | Expired |
| US6157210A | Programmable logic device with circuitry for observing programmable logic circuit signals and for preloading programmable logic circuits | Physics | 133 | Expired |
| US5963069A | System for distributing clocks using a delay lock loop in a programmable logic circuit | Electricity | 104 | Expired |
| US5909126A | Programmable logic array integrated circuit devices with interleaved logic array blocks | Electricity | 104 | Expired |
| US5894228A | Tristate structures for programmable logic devices | Electricity | 101 | Expired |
| US5982195A | Programmable logic device architectures | Electricity | 98 | Expired |
| US6107824A | Circuitry and methods for internal interconnection of programmable logic devices | Electricity | 97 | Expired |
| US6069487A | Programmable logic device circuitry for improving multiplier speed and/or efficiency | Electricity | 96 | Expired |
| US5498975A | Implementation of redundancy on a programmable logic device | Electricity | 95 | Expired |
| US6107820A | Redundancy circuitry for programmable logic devices with interleaved input circuits | Electricity | 94 | Expired |
| US6052327A | Dual-port programmable logic device variable depth and width memory array | Physics | 90 | Expired |
| US6130552A | Programmable logic integrated circuit with on-chip DLL or PLL for clock distribution | Electricity | 88 | Expired |
| US6467017B1 | Programmable logic device having embedded dual-port random access memory configurable as single-port memory | Physics | 87 | Expired |
| US6191998A | Programmable logic device memory array circuit having combinable single-port memory arrays | Physics | 87 | Expired |
| US5592102A | Means and apparatus to minimize the effects of silicon processing defects in programmable logic devices | Electricity | 84 | Expired |
| US5942914A | PLD with split multiplexed inputs from global conductors | Electricity | 83 | Expired |
| US5764080A | Input/output interface circuitry for programmable logic array integrated circuit devices | Electricity | 74 | Expired |
| US5847617A | Variable-path-length voltage-controlled oscillator circuit | Electricity | 68 | Expired |
| US6292016A | Programmable logic with on-chip DLL or PLL to distribute clock | Electricity | 68 | Expired |
| US5977793A | Programmable logic device with hierarchical interconnection resources | Electricity | 66 | Expired |
| US6049225A | Input/output interface circuitry for programmable logic array integrated circuit devices | Electricity | 65 | Expired |
| US5883526A | Hierarchical interconnect for programmable logic devices | Electricity | 64 | Expired |
| US6462577B1 | Configurable memory structures in a programmable logic device | Electricity | 61 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.