Method for driving bit line selecting signals
US5499218A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 1995 |
| Grant date | Mar 12, 1996 |
| Priority date | — |
| Expiry date | Jan 31, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for driving bit line selecting signals is disclosed, in which the DRAM cell includes a plurality of memory cell arrays, sense amplifiers, bit lines, bit line equalizer sections, bit line selecting sections, data input/output sections, and bit line selection signal generating sections. According to the present invention, the bit line selecting signals operate in such a manner that: during a bit line selection, a bit line selecting signal for connecting one pair of bit lines among the n pairs of bit lines to the sense amplifier is made to have a voltage level capable of connecting the bit lines to the sense amplifier by the help of the bit line selecting section without a voltage loss; the other bit line selecting signals corresponding to the non-selected remaining bit lines are given a voltage incapable of connecting the bit lines the sense amplifier by the bit line selecting section; thereafter, during the pre-charging for a bit line equalization, the bit line selecting signal corresponding to the bit line which was selected just before is given a voltage capable of connecting the bit lines to the sense amplifier by the help of the bit line selecting section; and the bit l…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.