Floating point register alias table FXCH and retirement floating point register array
US5499352A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 1993 |
| Grant date | Mar 12, 1996 |
| Priority date | — |
| Expiry date | Sep 30, 2013 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S707/99936
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Register Alias Table (RAT), including a retirement floating point RAT array, for floating point register renaming within a superscalar microprocessor capable of speculative execution. The RAT provides register renaming floating point registers to take advantage of a larger physical register set than would ordinarily be available within a given macroarchitecture's logical register set (such as the Intel architecture or PowerPC or Alpha designs) and thereby eliminate false data dependencies that reduce overall superscalar processing performance. As a set of uops is presented to the floating point RAT logic, their logical sources are used as indices into a floating point RAT array to look up the corresponding physical registers which reside within a Re-Order Buffer (ROB) where the data for these logical sources is found. An efficient FXCH operation is implemented within the floating point RAT mechanism by switching 6-bit physical register pointers rather than switching the actual data for each physical register which is 86-bits wide. There is a retirement floating point RAT array with dual valid bits and a dual TOS pointer to account for speculative FXCH operations in addition to an…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.