Apparatus and method for estimating time delays using unmapped combinational logic networks
US5500808A · kind A · utility
66Cited by
17References
21Claims
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Key dates
| Filing date | Mar 23, 1995 |
| Grant date | Mar 19, 1996 |
| Priority date | — |
| Expiry date | Mar 23, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A new method and structure are provided for simulating the time delay associated with signal propagation through a mapped and optimized logic network for a selected target technology using only information from an unmapped logic network. For each target technology, the method and structure include the time delay characteristics of the mapping and optimization strategies used to generate an optimized network using the library of standard gates for that target technology. The functional complexity of each unmapped logic node and the complexity of the fanout for each unmapped logic node are also included in the simulated time delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.