Integrated multichip memory module structure
US5502667A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 13, 1993 |
| Grant date | Mar 26, 1996 |
| Priority date | — |
| Expiry date | Sep 13, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19107
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated multichip memory module structure and method of fabrication wherein stacked semiconductor memory chips are integrated by a controlling logic chip such that a more powerful memory architecture is defined with the appearance of a single, higher level memory chip. A memory subunit is formed having N memory chips with each memory chip of the subunit having M memory devices. The controlling logic chip coordinates external communication with the N memory chips such that a single memory chip architecture with N.times.M memory devices appears at the module's I/O pins. A preformed electrical interface layer is employed at one end of the memory subunit to electrically interconnect the controlling logic chip with the memory chips comprising the subunit. The controlling logic chip has smaller dimensions than the dimensions of the memory chips comprising the subunit. A lead frame, having an inner opening extending therethrough, is secured to the electrical interface layer and the controlling logic chip is secured to the electrical interface layer so as to reside within the lead frame, thereby producing a dense multichip integrated circuit package. Corresponding fabrication techniq…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.