Asymmetric studs and connecting lines to minimize stress
US5504375A · kind A · utility
4Cited by
10References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 18, 1993 |
| Grant date | Apr 2, 1996 |
| Priority date | — |
| Expiry date | Nov 18, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In the design of stud and conducting line joints, the conducting line is extended beyond the stud without any significant overhang of the line in the width direction for minimizing induced stress in order to reduce voids and crack growth in the region where the connecting line is joined to the stud. The preferred length of the extension is in the range approximately between one-quarter and twice the stud dimension. The design is applicable, but not limited to, multilevel integrated circuits used in computers and other electrical devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.