Multi-level instruction boosting method using plurality of ordinary registers forming plurality of conjugate register pairs that are shadow registers to each other with different only in MSB
US5504914A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 23, 1993 |
| Grant date | Apr 2, 1996 |
| Priority date | — |
| Expiry date | Jun 23, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3842
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An instruction multi-level boosting method in a compiler has the step of providing a plurality of ordinary registers to act as the destination registers for access by the ordinary instructions. At least one instruction is boosted and speculatively executed. The boosting method also has the step of providing a plurality of special registers corresponding to the ordinary registers, and acting as the destination registers for access by the boosted and speculatively executed instruction. Then, at the original position of the boosted instruction, the address of at least one ordinary register used in the boosted instruction is translated into the address of at least one corresponding special register. In this way, the compiler efficiency can be incressed; the need of requiring additional registers is lowered; and the cost thereof is reduced down because no complicated duplicating circuit is needed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.