Double poly trenched channel accelerated tunneling electron (DPT-CATE) cell, for memory applications
US5506431A · kind A · utility
Inventor
Key dates
| Filing date | May 16, 1994 |
| Grant date | Apr 9, 1996 |
| Priority date | — |
| Expiry date | May 16, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/511
Abstract
A structure for low voltage, high density, non-volatile memory cell, with ability to write electrically using the CACT or Channel Accelerated Carrier Tunneling method for programming memories and erase electrically by tunneling, having separate regions for write and erase for high reliability, is described. These cells have the ability to write by transferring charge to the storage gate using the majority carriers in the channel of the MOS transistor, eliminating the need for generation of high fields needed for the hot electron EPROM write method used in the prior art flash memories. In addition the use of the carrier velocity to enhance the write process reduce the need for the high write -voltages on the gates as compared to the present EEPROM and EPROM write memories.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.