Low energy differential logic gate circuitry having substantially invariant clock signal loading
US5506519A · kind A · utility
5Cited by
4References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 3, 1994 |
| Grant date | Apr 9, 1996 |
| Priority date | — |
| Expiry date | Jun 3, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1738
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An energy efficient logic gate circuit design that provides a substantially constant load to a clock source regardless of logic signal inputs to, or outputs from, the gate. The gate provides two complementary outputs and utilizes cross-coupled transistors to ensure that the outputs remain valid (complementary) after the logic inputs become invalid. Two blocks, each having a node coupling to the clock source and performing complementary logic functions, in combination with diodes for recharging the outputs of the gate, present the constant load to the clock source.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.